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This document provides a flow for deriving a macro-model to allow the simulation of the conducted immunity levels of an Integrated circuit (IC). This model is intended to be used for predicting the immunity levels to conducted RF disturbances to integrated circuit pins.
Author | VDE |
---|---|
Editor | VDE |
Document type | Standard |
Format | Paper |
ICS | 31.200 : Integrated circuits. Microelectronics
33.100.20 : Immunity |
Number of pages | 106 |
Replace | DIN EN 62433-4 (2015-02) |
Cross references | EN 62433-4 (2016-10), IDT |
Weight(kg.) | 0.2802 |
Year | 2017 |
Document history | DIN EN 62433-4 (2017-05) |
Country | Germany |
Keyword | DIN EN 62433;EN 62433;EN 62433-4;62433 |